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⚡ Source: ReedRef: 57007934

Systems Test & Verification Engineer (Embedded Systems)

ZENOVO LTD·Bristol·Posted 1 week ago
🏢 On-site💰 £60-75k/year
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Job description

Original text imported from Reed

System Test & Verification Engineer (Hardware-in-the-Loop)
Location:
 Bristol– On-site 3 Days per Week
Salary:
 £60,000 – £75,000 + Bonus & Benefits (depending on experience)

Note: All applicants must be able to work in the UK without the need for VISA Sponsorship now, or in the future

Summary:   

A successful candidate will play a hands-on role in designing and implementing Hardware-in-the-Loop Simulations (HiLS) to test hardware and firmware.

They will take ownership of test strategy and execution for both legacy and new product developments, designing test cases, generating scenarios, and performing automated and manual testing to ensure solutions meet defined requirements.

Key Responsibilities

• Proven experience designing, implementing, and maintaining HiLS environments

• Developing and executing test plans, procedures, and test cases

• Integrating hardware with virtual models and simulation tools

• Investigating defects and collaborating with engineering teams to resolve issues

• Producing clear test documentation and reporting

• Experience with embedded development tools, debuggers, simulators, and automated test environments

• Ability to read and interpret hardware schematics and datasheets

Experience Required:
  • At least 3-years’ experience working with HiLS systems
  • Proven experience in HiLS testing
  • Experience with LabVIEW or MATLAB/Simulink
  • Ability to develop test cases using scripting languages (e.g. Python) and automation tools
  • Solid understanding of embedded systems, control systems, and system integration
  • Experience using version control systems (e.g. Git)
  • Proficient with Microsoft Windows and standard Office applications
  • Strong analytical and problem-solving skills
  • Degree in Computer Science, Electronic/Electrical Engineering, or a related field
Benefits Package
  • Competitive pension scheme (up to 7% employer matched)
  • Discretionary annual bonus (typically around 10%)
  • 25 days annual leave plus 8 bank holidays
  • Private medical healthcare
  • Hybrid working and flexitime
  • Annual wellness checks
  • Retail vouchers
  • Mental health support services

If you’re interested in learning more about this opportunity, please apply with your latest CV.
SpeedCV AI

Key skills

AI-extracted from the job advert

Must-have skills
Hardware-in-the-Loop (HiLS) simulation design and implementationLabVIEW or MATLAB/SimulinkPython test scriptingEmbedded systems and control systems knowledgeGit version controlHardware schematic and datasheet interpretationDegree in Computer Science, Electronic/Electrical Engineering or related field
Nice-to-have
Automated test environment configurationFirmware debugger and simulator toolingExperience with both legacy and new product development cycles
Soft skills
Analytical thinkingProblem solvingAttention to detailCollaborationOwnership and initiativeClear written communication
SpeedCV AI

Application advice

5 AI-generated recommendations to maximise your chances.

1

⭐ Lead your CV personal statement with 'Hardware-in-the-Loop' and 'HiLS' verbatim — the advert names these as the primary requirement and ATS will filter on exact match.

2

📊 Quantify your HiLS work: e.g. 'Designed and maintained a HiLS environment covering 12 ECU variants, reducing regression test cycle time by 35%' to stand out against candidates who list the skill without evidence.

3

🛠️ Create a dedicated 'Tools & Technologies' section listing LabVIEW, MATLAB/Simulink, Python, and Git explicitly — the advert calls each out by name and recruiters scan for them.

4

🎯 Include a bullet per role demonstrating test documentation output (test plans, defect reports, traceability matrices) as the advert specifically asks for 'clear test documentation and reporting'.

5

🌐 If you hold a degree in Electronic/Electrical Engineering or Computer Science, state the full title and classification in your Education section — the advert lists this as a baseline requirement and omitting it risks automatic rejection.

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Suggested CV bullets

3 bullets our AI drafted for this specific advert, mirroring its ATS keywords.

How to tailor your CV

Add these 3 bullets under your most recent experience:

  • Designed and maintained a HiLS test environment for 8 embedded control units using MATLAB/Simulink and LabVIEW, cutting hardware-dependent regression cycle time by 40% over 6 months.
  • Developed a Python-based automated test framework covering 350+ test cases for firmware validation, integrated with Git CI pipeline and reducing manual test effort by 60%.
  • Led test strategy and defect investigation for a legacy ECU migration programme, producing full traceability documentation and resolving 47 critical firmware defects ahead of a 12-week production deadline.

Free to copy — tailoring requires a 30-sec CV upload.

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AI cover letter

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Letter preview — tailored to ZENOVO LTD

Dear Hiring Manager,

Zenovo's focus on Hardware-in-the-Loop simulation and embedded firmware verification is precisely where I have built my career, which is why the Systems Test & Verification Engineer role in Bristol caught my attention immediately. With hands-on experience designing HiLS environments and developing automated test cases in Python and MATLAB/Simulink, I am confident I can take ownership of test strategy across both legacy and new product lines from day one.

My background in embedded systems testing includes integrating physical hardware with virtual models, maintaining version-controlled test suites in Git, and producing traceability documentation that satisfies rigorous verification requirements. I have collaborated closely with firmware and hardware engineering teams to investigate defects, reducing regression cycle times and improving first-pass yield on production builds.

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Interview questions

10 questions generated from this advert.

Technical

  • Walk us through how you would design a HiLS environment from scratch for a new embedded control system — what are the key integration steps?
  • How do you approach writing automated test cases in Python for firmware validation, and how do you manage test data versioning in Git?
  • Describe a scenario where you had to interpret hardware schematics to diagnose a failing test — what was your process?
  • How do you integrate virtual models built in MATLAB/Simulink with physical hardware in a HiLS rig, and what are the common pitfalls?
  • What strategies do you use to maintain HiLS test environments as firmware and hardware evolve across legacy and new product lines?

Behavioural

  • Tell me about a time you took full ownership of a test strategy for a complex embedded system — what decisions did you make and what was the outcome?
  • Describe a situation where you identified a critical defect late in the development cycle. How did you handle collaboration with the engineering team to resolve it?
  • Give an example of when you had to produce test documentation under time pressure. How did you ensure quality and clarity?
  • Tell me about a time your automated test suite produced unexpected results. How did you investigate and what did you learn?
  • Describe a situation where you had to balance testing legacy products alongside new development work. How did you prioritise?
SpeedCV AINEW

STAR answer examples

Model answers using the Situation-Task-Action-Result framework. Adapt to your own experience.

1Question

Tell me about a time you took full ownership of a test strategy for a complex embedded system — what decisions did you make and what was the outcome?

Situation: Our team was preparing to validate a new motor control firmware release with no existing automated test coverage — all prior testing had been manual and undocumented. Task: I was asked to own the entire test strategy from scratch within an 8-week window before the production sign-off gate. Action: I defined a three-tier strategy covering unit, integration, and HiLS-level tests, built a Python automation framework with 220 test cases, and integrated it into our Git CI pipeline using LabVIEW for signal injection. I also authored the traceability matrix linking each test to a system requirement. Result: We achieved 94% automated coverage, identified 18 defects before hardware build, and passed the sign-off gate one week ahead of schedule.
2Question

Describe a situation where you identified a critical defect late in the development cycle. How did you handle collaboration with the engineering team to resolve it?

Situation: During final HiLS regression testing, three weeks before customer delivery, I detected an intermittent timing fault in the CAN bus message handler that caused the control unit to enter a safe-state under high-load conditions. Task: I needed to characterise the fault precisely and work with the firmware team to deliver a verified fix without slipping the delivery date. Action: I reproduced the fault deterministically by scripting a Python load-injection scenario in the HiLS rig, captured the exact timing window, and shared a detailed defect report with oscilloscope traces and log files. I ran daily sync calls with the firmware lead to validate each patch iteration. Result: The root cause — a 2 ms timer overflow — was fixed and re-verified within five days, and the product shipped on schedule with zero field escapes reported in the first three months.

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